INTERRUPT CONTROLLER (ICU)
5.1 Outline of the Interrupt Controller
5
Interrupt Controller
System Break Interrupt (SBI)
request generated
(nonmaskable)
SBI Control Register
SBIREQ
(SBICR)
SBI
SBI#
To the CPU core
Peripheral circuits
Edge
Edge
Edge
Interrupt request
Interrupt request
Interrupt request
IREQ
IREQ
IREQ
External Interrupt (EI)
request generated
(maskable)
ILEVEL
Interrupt Vector Register
(IVECT)
EI
IMASK
compari-
son
To the CPU core
IREQ
Interrupt
Level
NEW_IMASK
control circuit
IREQ
IREQ
Interrupt
control circuit
Level
Level
Interrupt Request Mask
Register (IMASK)
Interrupt
control circuit
Interrupt Control Register
Figure 5.1.1 Block Diagram of the Interrupt Controller
32180 Group User’s Manual (Rev.1.0)
5-3
RENESAS [ RENESAS TECHNOLOGY CORP ]
