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M32180F8TFP 参数 Datasheet PDF下载

M32180F8TFP图片预览
型号: M32180F8TFP
PDF下载: 下载PDF文件 查看货源
内容描述: 32位RISC单芯片微型计算机M32R系列M32R / ECU系列 [32-Bit RISC Single-Chip Microcomputers M32R Family M32R/ECU Series]
分类和应用: 计算机
文件页数/大小: 839 页 / 3694 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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INTERRUPT CONTROLLER (ICU)  
5.1 Outline of the Interrupt Controller  
5
5.1 Outline of the Interrupt Controller  
The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break  
interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external  
interrupts (EI).  
The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels  
including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the  
same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request  
generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for  
internal peripheral I/Os.  
On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI#  
signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault  
condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register  
IE bit status. When the CPU has finished servicing an SBI, shut down or reset the system without returning to the  
program that was being executed when the interrupt occurred.  
Specifications of the Interrupt Controller are outlined below.  
Table 5.1.1 Outline of the Interrupt Controller (ICU)  
Item  
Specification  
Interrupt request source  
Maskable interrupt requests from internal peripheral I/Os: 32 sources (Note 1)  
System break interrupt request: 1 source (entered from SBI# pin)  
Priority management  
8 priority levels including an interrupt-disabled state  
(However, interrupts with the same priority level have their priorities resolved by fixed  
hardware priority.)  
Note 1: There are actually a total of 179 interrupt request resources when counted individually, which are grouped into 32  
interrupt request resources.  
32180 Group User’s Manual (Rev.1.0)  
5-2  
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