EIT
4.9 Interrupt Processing
4
Order in which instructions are executed
Address 1002 Address 1004 Address 1000
32-bit instruction
Address 1000
16-bit instruction 16-bit instruction
×
Interrupt may Interrupt cannot
Interrupt may
be accepted
Interrupt may
be accepted
be accepted
be accepted
Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted
[EIT Processing]
(1) Saving SM, IE and C bits
The PSW register’s SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC.
BSM ←
SM
IE
C
BIE
BC
←
←
(2) Updating SM, IE and C bits
The PSW register’s SM, IE and C bits are updated as shown below.
SM
IE
C
←
←
←
0
0
0
(3) Saving the PC
The address of the next instruction (always on word boundary) following one in which the interrupt was
detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then the next
instruction is one that exists at the jump address.
(4) Branching to the EIT vector entry
The CPU branches to the address H’0000 0010 in the user space. This is the last operation performed in
hardware preprocessing.
(5) Jumping from the EIT vector entry to the user-created handler
The CPU executes the BRA instruction written by the user at the address H’0000 0010 of the EIT vector
entry to jump to the start address of the user-created handler.
The system break interrupt can only be used when the system has some fatal event already existing in it
when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the
SBI handler, control will not return to the program that was being executed when the system break interrupt
occurred.
32180 Group User’s Manual (Rev.1.0)
4-16
RENESAS [ RENESAS TECHNOLOGY CORP ]
