Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N4)
1. Overview
1.2 Performance Overview
Table 1.1 lists the Functions and Specifications for M16C/6N Group (M16C/6N4).
Table 1.1 Functions and Specifications for M16C/6N Group (M16C/6N4)
Specification
Item
Normal-ver.
T/V-ver.
CPU
Number of fundamental
91 instructions
instructions
Minimum instruction
41.7 ns (f(BCLK) = 24 MHz,
50.0 ns (f(BCLK) = 20 MHz,
execution time
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Operating mode
Single-chip, memory expansion, and microprocessor modes
Address space
1 Mbyte
Memory capacity
Refer to
Table 1.2 Product Information
Peripheral Ports
Input/Output: 87 pins, Input: 1 pin
Function
Multifunction timers
Timer A: 16 bits
✕
5 channels
Timer B: 16 bits
✕
6 channels
Three-phase motor control circuit
Serial interfaces
3 channels
Clock synchronous, UART, I
2
C-bus
(1)
, IEBus
(2)
1 channel
Clock synchronous
A/D converter
10-bit A/D converter: 1 circuit, 26 channels
D/A converter
8 bits
✕
2 channels
DMAC
2 channels
CRC calculation circuit
CRC-CCITT
CAN module
2 channels with 2.0B specification
Watchdog timer
15 bits
✕
1 channel (with prescaler)
Interrupts
Internal: 31 sources, External: 9 sources
Software: 4 sources, Priority levels: 7 levels
Clock generation circuits 4 circuits
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with on-chip feedback resistor
Oscillation-stopped detector Main clock oscillation stop and re-oscillation detection function
VCC = 3.0 to 5.5 V (f(BCLK) = 24 MHz, VCC = 4.2 to 5.5 V (f(BCLK) = 20 MHz,
Electrical
Supply voltage
Characteristics
1/1 prescaler, without software wait) 1/1 prescaler, without software wait)
Consumption Mask ROM 20 mA (f(BCLK) = 24 MHz,
18 mA (f(BCLK) = 20 MHz,
current
PLL operation, no division)
PLL operation, no division)
Flash memory 22 mA (f(BCLK) = 24 MHz,
20 mA (f(BCLK) = 20 MHz,
PLL operation, no division)
PLL operation, no division)
Mask ROM 3 µA (f(BCLK) = 32 kHz, Wait mode, Oscillation capacity Low)
Flash memory 0.8 µA (Stop mode, Topr = 25°C)
Flash Memory Programming and erasure voltage 3.0 ± 0.3 V or 5.0 ± 0.5 V
5.0 ± 0.5 V
Version
Programming and erasure endurance 100 times
I/O
I/O withstand voltage
5.0 V
Characteristics Output current
5 mA
Operating Ambient Temperature
-40 to 85°C
T version: -40 to 85°C
V version: -40 to 125°C (option)
Device Configuration
CMOS high-performance silicon gate
Package
100-pin molded-plastic QFP, LQFP
NOTES:
1. I
2
C-bus is a trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a trademark of NEC Electronics Corporation.
option: All options are on request basis.
Rev.2.40 Aug 25, 2006
REJ03B0003-0240
page 2 of 88
RENESAS [ RENESAS TECHNOLOGY CORP ]
