Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N4)
4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
An SFR (Special Function Register) is a control register for a peripheral function.
Tables 4.1 to 4.16 list the SFR Information.
Table 4.1 SFR Information (1)
(3)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Processor Mode Register 0
(1)
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Chip Select Control Register
Address Match Interrupt Enable Register
Protect Register
Oscillation Stop Detection Register
(2)
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
Register
Symbol
After Reset
PM0
PM1
CM0
CM1
CSR
AIER
PRCR
CM2
WDTS
WDC
RMAD0
00000000b (CNVSS pin is "L")
00000011b (CNVSS pin is "H")
00001000b
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
0X000000b
XXh
00XXXXXXb
00h
00h
X0h
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
Chip Select Expansion Control Register
PLL Control Register 0
Processor Mode Register 2
CSE
PLC0
PM2
00h
0001X010b
XXX00000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DMA0 Source Pointer
SAR0
DMA0 Destination Pointer
DAR0
DMA0 Transfer Counter
TCR0
DMA0 Control Register
DM0CON
00000X00b
DMA1 Source Pointer
SAR1
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
DMA1 Destination Pointer
DAR1
DMA1 Transfer Counter
TCR1
DMA1 Control Register
DM1CON
00000X00b
X: Undefined
NOTES:
1. Bits PM00 and PM01 in the PM0 register do not change at software reset, watchdog timer reset and oscillation stop detection reset.
2. Bits CM20, CM21, and CM27 in the CM2 register do not change at oscillation stop detection reset.
3. Blank spaces are reserved. No access is allowed.
Rev.2.40 Aug 25, 2006
REJ03B0003-0240
page 15 of 88
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