Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6N4)
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R3
R0H (R0's high bits) R0L (R0's low bits)
R1H (R1's high bits) R1L (R1's low bits)
R2
R3
A0
A1
FB
b19
b15
b0
Data Registers
(1)
Address Registers
(1)
Frame Base Registers
(1)
INTBH
INTBL
Interrupt Table Register
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
b0
PC
b15
b0
Program Counter
USP
ISP
SB
b15
b0
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
FLG
b15
b8 b7
b0
Flag Register
IPL
U
I
O B S
Z
D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is analogous to R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.2.40 Aug 25, 2006
REJ03B0003-0240
page 12 of 88
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