M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.29
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Standard
Symbol
Parameter
Unit
Min.
Max.
25
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
4
(NOTE 1)
(NOTE 1)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
25
Chip Select Output Hold Time (in relation to BCLK)
Chip Select Output Hold Time (in relation to RD)
Chip Select Output Hold Time (in relation to WR)
RD Signal Output Delay Time
4
(NOTE 1)
(NOTE 1)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
25
40
RD Signal Output Hold Time
0
0
WR Signal Output Delay Time
WR Signal Output Hold Time
See
Figure 5.2
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
4
(NOTE 2)
(NOTE 1)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(AD-ALE)
td(AD-RD)
40
15
ALE Signal Output Delay Time (in relation to BCLK)
ALE Signal Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time (in relation to Address)
ALE Signal Output Hold Time (in relation to Address)
RD Signal Output Delay From the End of Address
WR Signal Output Delay From the End of Address
Address Output Floating Start Time
−4
(NOTE 3)
(NOTE 4)
0
0
td(AD-WR)
tdz(RD-AD)
8
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 10[ns]
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
(n – 0.5)x10
f(BCLK)
------------------------------------ – 40 [n s ]
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 25[ns]
f(BCLK)
4. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 15[ns]
f(BCLK)
Rev.2.41 Jan 10, 2006 Page 55 of 96
REJ03B0001-0241
RENESAS [ RENESAS TECHNOLOGY CORP ]
