M16C/62 Group (M16C/62P, M16C/62PT)
1. Overview
1.3 Block Diagram
Figure 1.1 is a block diagram of the M16C/62 group (M16C/62P, M16C/62PT) 128-pin and 100-pin version,
figure 1.2 is a block diagram of the M16C/62 group (M16C/62P, M16C/62PT) 80-pin version.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
<VCC1 ports>
(4)
Port P7
<VCC2 ports>
(4)
Internal peripheral functions
8
A-D converter
Timer (16-bit)
Output (timer A): 5
Input (timer B): 6
Three-phase motor
control circuit
(10 bits
X
8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
Ring oscillator
Clock synchronous serial I/O
Port P8
7
(8 bits
X
3 channels)
CRC arithmetic circuit (CCITT )
(Polynomial : X
16
+X
12
+X
5
+1)
<VCC1 ports>
(4)
Port P8_5
(8 bits
X
2 channels)
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
R0H
R1H
R2
R3
A0
A1
FB
R0L
R1L
SB
USP
ISP
INTB
PC
FLG
Memory
ROM
(1)
RAM
(2)
Port P9
8
DMAC
(2 channels)
Port P10
D-A converter
(8 bits X 2 channels)
8
Multiplier
<VCC1 ports>
(4)
Port P11
(3)
<VCC2 ports>
(4)
Port P12
(3)
Port P14
(3)
Port P13
(3)
8
2
8
8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1 M16C/62 Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Rev.2.10 Nov. 07, 2003 page 5
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RENESAS [ RENESAS TECHNOLOGY CORP ]
