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M30626FJPGP 参数 Datasheet PDF下载

M30626FJPGP图片预览
型号: M30626FJPGP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位CMOS微机 [SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER]
分类和应用: 外围集成电路微控制器计算机时钟
文件页数/大小: 87 页 / 832 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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5. Electrical Characteristics (M16C/62P)  
M16C/62 Group (M16C/62P, M16C/62PT)  
(1)  
Table 5.4 A-D Conversion Characteristics  
Standard  
Min. Typ. Max.  
10  
Symbol  
Parameter  
Measuring condition  
Unit  
Bits  
Resolution  
V
REF =VCC1  
AN0 to AN7 input  
V
V
5V  
REF  
=
=
AN0_0 to AN0_7 input  
AN2_0 to AN2_7 input  
ANEX0, ANEX1 input  
CC1  
±3  
±7  
LSB  
LSB  
Integral  
non-  
linearity  
error  
INL  
10 bit  
External operation amp  
connection mode  
AN0 to AN7 input  
V
V
3.3V  
REF  
=
=
AN0_0 to AN0_7 input  
AN2_0 to AN2_7 input  
ANEX0, ANEX1 input  
CC1  
±5  
LSB  
External operation amp  
connection mode  
±7  
±2  
LSB  
LSB  
V
REF =VCC1=3.3V  
8 bit  
AN0 to AN7 input  
V
V
5V  
REF  
=
=
AN0_0 to AN0_7 input  
AN2_0 to AN2_7 input  
ANEX0, ANEX1 input  
CC1  
±3  
±7  
LSB  
LSB  
Absolute  
accuracy  
10 bit  
External operation amp  
connection mode  
AN0 to AN7 input  
V
V
3.3V  
REF  
=
=
AN0_0 to AN0_7 input  
AN2_0 to AN2_7 input  
ANEX0, ANEX1 input  
CC1  
±5  
LSB  
External operation amp  
connection mode  
±7  
±2  
LSB  
LSB  
V
REF =VCC1=3.3V  
8 bit  
DNL  
Tolerance level impedance  
Differential non-linearity error  
Offset error  
3
kΩ  
LSB  
LSB  
LSB  
kΩ  
±1  
±3  
±3  
Gain error  
Ladder resistance  
10  
40  
R
LADDER  
VREF =VCC1  
Conversion time(10bit), Sample & hold  
function available  
2.75  
t
CONV  
V
REF =VCC1=5V, øAD=12MHz  
µs  
Conversion time(8bit), Sample & hold  
function available  
2.33  
0.25  
t
t
V
V
CONV  
SAMP  
V
REF =VCC1=5V, øAD=12MHz  
µs  
Sampling time  
µs  
V
REF  
IA  
Reference voltage  
Analog input voltage  
2.0  
0
V
CC1  
V
V
REF  
NOTES:  
1. Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise  
specified.  
2. If VCC1 > VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.  
3. AD operation clock frequency (øAD frequency) must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V,  
and øAD frequency into 10 MHz or less.  
4. A case without sample & hold function turn øAD frequency into 250 kHz or more in addition to a limit of Note 3.  
A case with sample & hold function turn øAD frequency into 1MHz or more in addition to a limit of Note 3.  
(1)  
Table 5.5 D-A Conversion Characteristics  
Standard  
Min. Typ. Max.  
8
Symbol  
Parameter  
Measuring condition  
Unit  
Bits  
%
Resolution  
1.0  
3
Absolute accuracy  
t
su  
µs  
Setup time  
R
O
4
10  
20  
kΩ  
Output resistance  
I
VREF  
(Note 2)  
1.5  
mA  
Reference power supply input current  
NOTES:  
1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.  
2. This applies when using one D-A converter, with the D-A register for the unused D-A converter set to 00h. The A-D  
converters ladder resistance is not included. Also, when D-A register contents are not 00h, the current IVREF always  
flows even though Vref may have been set to be unconnected by the A-D control register.  
page 33  
Rev.2.10 Nov. 07, 2003  
of 84  
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