HN58V65A Series, HN58V66A Series
Write Cycle 1
(2.7 V
≤
V
CC
<
4.5 V)
Parameter
Address setup time
Address hold time
CE
to write setup time (WE controlled)
CE
hold time (WE controlled)
WE
to write setup time (CE controlled)
WE
hold time (CE controlled)
OE
to write setup time
OE
hold time
Data setup time
Data hold time
WE
pulse width (WE controlled)
CE
pulse width (CE controlled)
Data latch time
Byte load cycle
Byte load window
Write cycle time
Time to device busy
Write start time
Reset protect time*
Reset high time*
2, 6
2
Symbol
t
AS
t
AH
t
CS
t
CH
t
WS
t
WH
t
OES
t
OEH
t
DS
t
DH
t
WP
t
CW
t
DL
t
BLC
t
BL
t
WC
t
DB
t
DW
t
RP
t
RES
Min*
0
50
0
0
0
0
0
0
50
0
200
200
100
0.3
100
—
120
0*
1
5
3
Typ
Max
30
10*
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ms
ns
ns
µs
µs
Test conditions
100
Notes: 1. t
DF
and t
DFR
are defined as the time at which the outputs achieve the open circuit conditions and
are no longer driven.
2. This function is supported by only the HN58V66A series.
3. Use this device in longer cycle than this value.
4. t
WC
must be longer than this value unless polling techniques or RDY/Busy are used. This device
automatically completes the internal write operation within this value.
5. Next read or write operation can be initiated after t
DW
if polling techniques or RDY/Busy are used.
6. This parameter is sampled and not 100% tested.
7. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
WE.
8. A6 through A12 are page addresses and these addresses are latched at the first falling edge of
CE.
9. See AC read characteristics.
Rev.3.00, Dec. 04.2003, page 9 of 26
RENESAS [ RENESAS TECHNOLOGY CORP ]
