HD74LS194A
Function Table
Clear
L
H
H
H
H
H
H
H
Notes: 1.
2.
3.
4.
Mode
S
1
X
X
H
L
L
H
H
L
S
0
X
X
H
H
H
L
L
L
Clock
X
L
↑
↑
↑
↑
↑
X
Inputs
Serial
Left
Right
X
X
X
X
X
X
X
H
X
L
H
X
L
X
X
X
Outputs
A
X
X
a
X
X
X
X
X
Parallel
B
C
X
X
X
X
b
c
X
X
X
X
X
X
X
X
X
X
D
X
X
d
X
X
X
X
X
Q
A
L
Q
A0
a
H
L
Q
Bn
Q
Bn
Q
Ao
Q
B
L
Q
B0
b
Q
An
Q
An
Q
Cn
Q
Cn
Q
Bo
Q
C
L
Q
C0
c
Q
Bn
Q
Bn
Q
Dn
Q
Dn
Q
Co
Q
D
L
Q
D0
d
Q
Cn
Q
Cn
H
L
Q
Do
H; high level, L; low level, X; irrelevant
↑;
transition from low to high level
a to d; the level of steady-state input at inputs A, B, C, or D, respectively
Q
A0
to Q
D0
; the level of Q
A
, Q
B
, Q
C
, or Q
D
, respectively before the indicated steady-state input conditions were
established.
5. Q
An
to Q
Dn
; the level of Q
A
, Q
B
, Q
C
, or Q
D
, respectively before the most-recent
↑
transition of the clock.
Block Diagram
Parallel Inputs
A
B
C
D
Mode
Control
Inputs
S
1
S
0
Shift
Right
Serial
Input
Shift
Left
Serial
Input
S Q
A
CK
R
Clear
S Q
B
CK
R
Clear
S Q
C
CK
R
Clear
S Q
D
CK
R
Clear
Clock
Clear
Q
A
Q
B
Q
C
Q
D
Parallel Outputs
Rev.3.00, Jul.15.2005, page 2 of 7
RENESAS [ RENESAS TECHNOLOGY CORP ]
