HD74LS194A
4-bit Bidirectional Universal Shift Register
REJ03D0456–0300
Rev.3.00
Jul.15.2005
The bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a
shift register. The circuit contains 46 equivalent gates and features parallel inputs, parallel outputs, right-shift and left-
shift serial inputs. Operating-mode-control inputs, and a direct overriding clear line. The register has four distinct
modes of operation, namely;
•
•
•
•
Parallel (broadside) load
Shift right (in the direction Q
A
toward Q
D
)
Shift left (in the direction Q
D
toward Q
A
)
Inhibit clock (do nothing)
Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S
0
and S
1
, high. The data are loaded into the associated flip-flops and appear at the outputs after the positive transition of
the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising
edge of the clock pulse when S
0
is high and S
1
is low. Serial data for this mode is entered at the shift-right data input.
When S
0
is low and S
1
is high, data shifts left synchronously and new data is entered at the shift-left serial input.
Clocking of the flip-flop is inhibited when both mode control inputs are low.
•
Ordering Information
Part Name
HD74LS194AP
HD74LS194AFPEL
Package Type
DILP-16 pin
SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
Package
Abbreviation
P
Taping Abbreviation
(Quantity)
—
EL (2,000 pcs/reel)
PRSP0016DH-B
FP
(FP-16DAV)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
Clear
Shift Right
Serial Input
A
Parallel
Inputs
B
C
D
Shift Left
Serial Input
GND
1
CLR
2
3
4
5
6
7
8
R
A
B
C
D
L
S
0
Q
A
Q
B
Q
C
Q
D
CK
S
1
16
15
14
13
12
11
10
9
V
CC
Q
A
Q
B
Q
C
Q
D
Clock
S
1
S
0
Mode
Control
Parallel
Outputs
(Top view)
Rev.3.00, Jul.15.2005, page 1 of 7
RENESAS [ RENESAS TECHNOLOGY CORP ]
