HD74LS166A
Waveform
t
w (Clear)
3V
Clear
Input
1.3V
1.3V
0V
t
n
t
n
+ 1
Clock
Input
t
n
t
n
+ 1
3V
1.3V
t
w (Clock)
Data
Input
t
PHL
Output Q
H
1.3V
1.3V
t
su
1.3V
t
h
1.3V
t
PLH
1.3V
t
PHL
V
OH
1.3V
1.3V
1.3V
V
OL
t
su
1.3V
0V
t
h
3V
1.3V
0V
Notes:
1. Input pulse;
≤
15 ns, t
THL
≤
6 ns, PRR = 1 MHz, duty cycle 50%
Clock input; t
w
≥
20 ns
Clear inpu; t
w
≥
20 ns, t
h
= 10 ns, when testing
ƒ
max
, vary the clock PRR.
2. Propagation delay time (t
PLH
and t
PHL
) are measured at t
n + 1
. Proper shifting of data is verified
at t
n + 8
with a functional test.
3. t
n
; bit time before clocking transition.
t
n + 1
; bit time after one clocking transition.
t
n + 8
; bit time after eight clocking transition.
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
Clock
Clock Inhibit
Clear
Serial Input
Shift / Load
A
B
C
Parallel
Inputs
D
E
F
G
H
Output Q
H
H
L
H
L
H
L
H
H
H
H
L
H
L
H
L
H
L
Clear
Serial Shift
Load Inhibit
Serial Shift
Rev.4.00, May 10, 2006, page 6 of 7
RENESAS [ RENESAS TECHNOLOGY CORP ]
