HD74LS166A
Function Table
Inputs
Clear
L
H
H
H
H
H
Shift
Load
X
X
L
H
H
X
Clock
Inhibit
X
L
L
L
L
H
Clock
X
L
↑
↑
↑
↑
Serial
X
X
X
H
L
X
Parallel
A…H
X
X
a…h
X
X
X
Internal outputs
Q
A
L
Q
A0
a
H
L
Q
A0
Q
B
L
Q
B0
b
Q
An
Q
An
Q
B0
Output
Q
H
L
Q
H0
h
Q
Gn
Q
Gn
Q
H0
Notes: 1. H; high level, L; low level, X; irrelevant
2.
↑;
transition from low to high level
3. a to h; the level of steady-state input at inputs A to H respectively
4. Q
A0
to Q
H0
; the level of Q
A
to Q
H
, respectively, before the indicated steady-state input conditions were
established.
5. Q
An
to Q
Gn
; the level of Q
A
to Q
G
, respectively, before the most recent
↑
transition of the clock.
Rev.4.00, May 10, 2006, page 2 of 7
RENESAS [ RENESAS TECHNOLOGY CORP ]
