欢迎访问ic37.com |
会员登录 免费注册
发布采购

HD64F3337YF16 参数 Datasheet PDF下载

HD64F3337YF16图片预览
型号: HD64F3337YF16
PDF下载: 下载PDF文件 查看货源
内容描述: 单片机 [Single-Chip Microcomputer]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 747 页 / 2993 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号HD64F3337YF16的Datasheet PDF文件第214页浏览型号HD64F3337YF16的Datasheet PDF文件第215页浏览型号HD64F3337YF16的Datasheet PDF文件第216页浏览型号HD64F3337YF16的Datasheet PDF文件第217页浏览型号HD64F3337YF16的Datasheet PDF文件第219页浏览型号HD64F3337YF16的Datasheet PDF文件第220页浏览型号HD64F3337YF16的Datasheet PDF文件第221页浏览型号HD64F3337YF16的Datasheet PDF文件第222页  
Increment Caused by Changing of Internal Clock Source: When an internal clock source is  
changed, the changeover may cause FRC to increment. This depends on the time at which the  
clock select bits (CKS1 and CKS0) are rewritten, as shown in table 8.5.  
The pulse that increments FRC is generated at the falling edge of the internal clock source. If  
clock sources are changed when the old source is high and the new source is low, as in case no. 3  
in table 8.5, the changeover generates a falling edge that triggers the FRC increment clock pulse.  
Switching between an internal and external clock source can also cause FRC to increment.  
Table 8.5 Effect of Changing Internal Clock Sources  
No.  
Description  
Timing  
1
Low low:  
Old clock  
source  
CKS1 and CKS0 are  
rewritten while both  
clock sources are low.  
New clock  
source  
FRC clock  
pulse  
N + 1  
FRC  
N
CKS rewrite  
2
Low high:  
CKS1 and CKS0 are  
rewritten while old  
Old clock  
source  
clock source is low and  
new clock source is high.  
New clock  
source  
FRC clock  
pulse  
N
N + 1  
N + 2  
FRC  
CKS rewrite  
188  
 复制成功!