Contention between OCR Write and Compare-Match: If a compare-match occurs during the
T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes priority and the
compare-match signal is inhibited.
Figure 8.18 shows this type of contention.
Write cycle:
CPU write to lower byte of OCRA or OCRB
T1
T2
T3
ø
Internal address bus
OCR address
Internal write signal
FRC
N
N + 1
OCRA or OCRB
N
M
Write data
Compare-match
A or B signal
Inhibited
Figure 8.18 Contention between OCR Write and Compare-Match
187