Contents
Section 1 Overview...........................................................................................................
1.1 Overview............................................................................................................................
1.2 Block Diagram...................................................................................................................
1.3 Pin Assignments and Functions.........................................................................................
1.3.1 Pin Arrangement ..................................................................................................
1
1
6
8
8
1.3.2 Pin Functions........................................................................................................ 12
Section 2 CPU....................................................................................................................... 25
2.1 Overview............................................................................................................................ 25
2.1.1 Features ................................................................................................................ 25
2.1.2 Address Space ...................................................................................................... 26
2.1.3 Register Configuration ......................................................................................... 26
2.2 Register Descriptions......................................................................................................... 27
2.2.1 General Registers.................................................................................................. 27
2.2.2 Control Registers.................................................................................................. 27
2.2.3 Initial Register Values.......................................................................................... 28
2.3 Data Formats...................................................................................................................... 29
2.3.1 Data Formats in General Registers....................................................................... 30
2.3.2 Memory Data Formats.......................................................................................... 31
2.4 Addressing Modes ............................................................................................................. 32
2.4.1 Addressing Mode.................................................................................................. 32
2.4.2 Calculation of Effective Address.......................................................................... 34
2.5 Instruction Set.................................................................................................................... 38
2.5.1 Data Transfer Instructions.................................................................................... 40
2.5.2 Arithmetic Operations.......................................................................................... 42
2.5.3 Logic Operations.................................................................................................. 43
2.5.4 Shift Operations.................................................................................................... 43
2.5.5 Bit Manipulations................................................................................................. 45
2.5.6 Branching Instructions.......................................................................................... 50
2.5.7 System Control Instructions ................................................................................. 52
2.5.8 Block Data Transfer Instruction ........................................................................... 53
2.6 CPU States......................................................................................................................... 55
2.6.1 Overview .............................................................................................................. 55
2.6.2 Program Execution State...................................................................................... 56
2.6.3 Exception-Handling State .................................................................................... 56
2.6.4 Power-Down State................................................................................................ 57
2.7 Access Timing and Bus Cycle........................................................................................... 57
2.7.1 Access to On-Chip Memory (RAM and ROM) ................................................... 57
2.7.2 Access to On-Chip Supporting Modules and External Devices .......................... 59
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RENESAS [ RENESAS TECHNOLOGY CORP ]
