7.2.2
Register Configuration and Descriptions
Table 7.2 summarizes the port 1 registers.
Table 7.2 Port 1 Registers
Name
Abbreviation
Read/Write Initial Value
Address
Port 1 data direction register
P1DDR
W
H'FF (mode 1)
H'FFB0
H'00 (modes 2 and 3)
Port 1 data register
P1DR
R/W
R/W
H'00
H'00
H'FFB2
H'FFAC
Port 1 input pull-up control
register
P1PCR
Port 1 Data Direction Register (P1DDR)
Bit
7
6
5
4
3
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Mode 1
Initial value
1
1
1
1
1
1
1
1
Read/Write
Modes 2 and 3
Initial value
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P1DDR controls the input/output direction of each pin in port 1.
Mode 1: The P1DDR values are fixed at 1. Port 1 consists of lower address output pins. P1DDR
values cannot be modified and are always read as 1.
In hardware standby mode, the address bus is in the high-impedance state.
Mode 2: A pin in port 1 is used for address output if the corresponding P1DDR bit is set to 1, and
for general input if this bit is cleared to 0.
Mode 3: A pin in port 1 is used for general output if the corresponding P1DDR bit is set to 1, and
for general input if this bit is cleared to 0.
In modes 2 and 3, P1DDR is a write-only register. Read data is invalid. If read, all bits always read
1. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby
mode it retains its existing values, so if a transition to software standby mode occurs while a
P1DDR bit is set to 1, the corresponding pin remains in the output state.
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