Section
22.7.4 Erase-Verify
Mode
Figure 22.14
Erase/Erase-Verify
Flowchart
Page
713
Description
Figure amended
Start
*1
Set SWE bit in FLMCR1
Wait 10
µs
n=1
Set EBR1(2)
Enable WDT
Set ESU1(2) bit in FLMCR1(2)
Wait 200
µs
Set E1(2) bit in FLMCR1(2)
Wait 5 ms
Clear E1(2) bit in FLMCR1(2)
Wait 10
µs
Clear ESU1(2) bit in FLMCR1(2)
Wait 10
µs
Disable WDT
Set EV1(2) bit in FLMCR1(2)
Wait 20
µs
Set block start address to verify address
*5
n
←
n+1
*5
*5
Start erase
*5
Halt erase
*5
*3
*5
H'FF dummy write to verify address
Wait 2
µs
Increment
address
Read verify data
Verify data = all "1"?
OK
NG
Last address of block?
OK
Clear EV1(2) bit in FLMCR1(2)
Wait 5
µs
NG
*4
End of
erasing of all erase
blocks?
OK
*5
Clear EV1(2) bit in FLMCR1(2)
Wait 5
µs
*5
n
≥
60?
OK
Clear SWE bit in FLMCR1
Erase failure
NG
*5
*5
*2
NG
Clear SWE bit in FLMCR1
End of erasing
Notes:
*1
*2
*3
*4
*5
Preprogramming (setting erase block data to all “0”) is not necessary.
Verify data is read in 32-bit (longword) units.
Set only one bit in EBR1(2). More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, each block must be erased in turn.
Make sure to set the wait times and repetitions as specified. Erasing may not complete correctly if values other
than the specified ones are used.
24.4.2 Canceling the 747
Standby Mode
Cancellation by a Manual Reset deleted
25. Electrical
Characteristics (5V,
33.3 MHz Version)
—
Deleted
RENESAS [ RENESAS TECHNOLOGY CORP ]
