Section
22.7.2 Program-
Verify Mode
Figure 22.13
Program/Program
Verify Flow
Page
706
Description
Figure amended
Start
Set SWE bit in FLMCR1
Wait 10
µs
Store 32-byte program data in
reprogram data area
n
=
1
*
5
*
4
m=0
Write 32-byte data in reprogram data area
in RAM to flash memory consecutively
Enable WDT
Set PSU1(2) bit in FLMCR1(2)
Wait 50
µs
Set P1(2) bit in FLMCR1(2)
Wait 200
µs
Clear P1(2) bit in FLMCR1(2)
Wait 10
µs
Clear PSU1(2) bit in FLMCR1(2)
Wait 10
µs
Disable WDT
Set PV1(2) bit in FLMCR1(2)
Wait 4
µs
*
1
*
5
Start of programming
*
5
End of programming
*
5
*
5
*
5
n
←
n+1
Dummy write of H'FF to verify address
Wait 2
µs
Read verify data
*
5
*
2
*
3
Verify
Increment address
Program data = verify data?
OK
Reprogram data computation
Transfer reprogram data to reprogram
data area
NG
m=1
*
3
*
4
NG
End of 32-byte
data verification?
OK
Clear PV1(2) bit in FLMCR1(2)
Wait 4
µs
flag = 0?
OK
Clear SWE bit in FLMCR1
*
5
NG
*
5
n
≥
1000
*5
OK
Clear SWE bit in FLMCR1
NG
End of programming
Programming failure
Note
*5
added.
*5
Make sure to set the wait times and repetitions as specified.
Programming may not complete correctly if values other than
the specified ones are used.
RENESAS [ RENESAS TECHNOLOGY CORP ]
