Section 21 List of Registers
Register
Name
Reset
Active
Sleep
Subactive Subsleep Standby
Module
IEGR1
IEGR2
IENR1
IENR2
IRR1
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Interrupt
IRR2
IWPR
MSTCR1
MSTCR2
Low power
Notes: is not initialized
1. WDT: Watchdog timer
2. The BARE register is only provided for microcontrollers that support advanced mode.
Rev. 3.00 Sep. 10, 2007 Page 413 of 528
REJ09B0216-0300