Section 21 List of Registers
Register
Name
Reset
Active
Sleep
Subactive Subsleep Standby
Module
FLMCR1
FLMCR2
FLPWCR
EBR1
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
ROM
Initialized
Initialized
Initialized
FENR
TCRV0
TCSRV
TCORA
TCORB
TCNTV
TCRV1
SMR
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Initialized
Timer V
SCI3
BRR
SCR3
TDR
SSR
RDR
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
ADCR
A/D converter
PWDRL
PWDRU
PWCR
TCSRWD
TCWD
TMWD
ABRKCR
ABRKSR
14bit PWM
WDT*1
Address break
Rev. 3.00 Sep. 10, 2007 Page 411 of 528
REJ09B0216-0300