Section 21 List of Registers
21.1
Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Data
Abbre-
Module
Bus
Access
Register
viation Bit No Address Name
Width State
H'F000
to
H'F6FF
Timer control register_0
TCR_0
8
H'F700 Timer Z
H'F701 Timer Z
H'F702 Timer Z
H'F703 Timer Z
H'F704 Timer Z
H'F705 Timer Z
8
8
8
8
8
8
2
2
2
2
2
2
Timer I/O control register A_0
Timer I/O control register C_0
Timer status register_0
TIORA_0 8
TIORC_0 8
TSR_0
TIER_0
8
8
Timer interrupt enable register_0
PWM mode output level control
register_0
POCR_0 8
Timer counter_0
TCNT_0 16
GRA_0 16
GRB_0 16
GRC_0 16
GRD_0 16
H'F706 Timer Z
H'F708 Timer Z
H'F70A Timer Z
H'F70C Timer Z
H'F70E Timer Z
H'F710 Timer Z
H'F711 Timer Z
H'F712 Timer Z
H'F713 Timer Z
H'F714 Timer Z
H'F715 Timer Z
16
16
16
16
16
8
2
2
2
2
2
2
2
2
2
2
2
General register A_0
General register B_0
General register C_0
General register D_0
Timer control register_1
Timer I/O control register A_1
Timer I/O control register C_1
Timer status register_1
Timer interrupt enable register_1
TCR_1
8
TIORA_1 8
TIORC_1 8
8
8
TSR_1
TIER_1
8
8
8
8
PWM mode output level control
register_1
POCR_1 8
8
Timer counter_1
TCNT_1 16
GRA_1 16
GRB_1 16
H'F716 Timer Z
H'F718 Timer Z
H'F71A Timer Z
16
16
16
2
2
2
General register A_1
General register B_1
Rev. 3.00 Sep. 10, 2007 Page 396 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
