Section 18 A/D Converter
18.3
Register Descriptions
The A/D converter has the following registers.
•
•
•
•
•
•
A/D data register A (ADDRA)
A/D data register B (ADDRB)
A/D data register C (ADDRC)
A/D data register D (ADDRD)
A/D control/status register (ADCSR)
A/D control register (ADCR)
18.3.1
A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each analog input
channel, are shown in table 18.2.
The converted 10-bit data is stored in bits 15 to 6. The lower 6 bits are always read as 0.
The data bus width between the CPU and the A/D converter is 8 bits. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are transferred from the ADDR when the upper byte data is read.
When reading ADDR, read the upper byte first then the lower one, or read in word units. The
ADDR is initialized to H'0000.
Table 18.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0
AN0
Group 1
AN4
A/D Data Register to Be Stored Results of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
AN1
AN5
AN2
AN6
AN3
AN7
Rev. 3.00 Sep. 10, 2007 Page 370 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
