Section 17 I2C Bus Interface 2 (IIC2)
17.7.3
Restriction in Use of Multi-Master
(1) Restriction on Setting Transfer Rate
In multi-master usage when I2C transfer rate setting of this LSI is lower than those of the other
masters, unexpected length of SCL may occasionally be output. To avoid this, the specified value
must be greater than or equal to the value produced by multiplying the fastest transfer rate among
the other masters by 1/1.8. For example, when the transfer rate of the fastest bus master among the
other bus masters is 400 kbps, the transfer rate of the I2C of this LSI must be set to at least
223 kbps (= 400/1.8).
(2) Restriction on Use of Bit Manipulation Instructions to Set MST and TRS
When master transmission is selected by consecutively manipulating the MST and TRS bits in
multi-master usage, an arbitration loss during execution of the bit-manipulation instruction for
TRS leads to the contradictory situation where AL in ICSR is 1 in master transmit mode (MST =
1, TRS = 1).
Ways to avoid this effect are listed below.
•
•
Use the MOV instruction to set MST and TRS in multi-master usage.
When arbitration is lost, confirm that MST = 0 and TRS = 0. If the setting of MST = 0 and
TRS = 0 is not confirmed, set MST = 0 and TRS = 0 again.
17.7.4
Continuous Data Reception in Master Receive Mode
In master receive mode, when SCL is fixed low on the falling edge of the 8th clock while the
RDRF bit is set to 1 and ICDRR is read around the falling edge of the 8th clock, the clock is only
fixed low in the 8th clock of the next round of data reception. The SCL is then released from its
fixed state without reading ICDRR and the 9th clock is output. As a result, some receive data is
lost.
Ways to avoid this phenomenon are listed below.
•
•
Read ICDRR in master receive mode before the rising edge of the 8th clock.
Set RCVD to 1 in master receive mode and perform communication in units of one byte.
Rev. 3.00 Sep. 10, 2007 Page 365 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
