Section 17 I2C Bus Interface 2 (IIC2)
17.6
Bit Synchronous Circuit
In master mode, this module has a possibility that high level period may be short in the two states
described below.
•
•
When SCL is driven to low by the slave device
When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-
up resistance)
Therefore, it monitors SCL and communicates by bit with synchronization.
Figure 17.21 shows the timing of the bit synchronous circuit and table 17.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
VIH
SCL
Internal SCL
Figure 17.21 The Timing of the Bit Synchronous Circuit
Table 17.4 Time for Monitoring SCL
CKS3
CKS2
Time for Monitoring SCL
7.5 tcyc
0
0
1
0
1
19.5 tcyc
1
17.5 tcyc
41.5 tcyc
Rev. 3.00 Sep. 10, 2007 Page 363 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
