Section 16 Serial Communication Interface 3 (SCI3)
Table 16.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency φ (MHz)
2
2.097152
Error
(%)
2.4576
Error
(%)
3
Bit Rate
(bits/s)
Error
(%)
Error
(%)
n
1
1
0
0
0
0
0
0
0
0
0
N
n
1
1
0
0
0
0
0
0
0
0
0
N
n
1
1
0
0
0
0
0
0
0
0
0
N
n
1
1
1
0
0
0
0
0
0
0
—
N
110
141 0.03
103 0.16
207 0.16
103 0.16
148 –0.04
108 0.21
217 0.21
108 0.21
174 –0.26
127 0.00
255 0.00
127 0.00
212 0.03
155 0.16
150
300
77
0.16
600
155 0.16
1200
2400
4800
9600
19200
31250
38400
51
25
12
6
0.16
54
26
13
6
–0.70
1.14
63
31
15
7
0.00
0.00
0.00
0.00
0.00
22.88
0.00
77
38
19
9
0.16
0.16
–2.34
–2.34
–2.34
0.00
—
0.16
0.16
–2.48
–2.48
13.78
4.86
–6.99
8.51
2
2
3
4
1
0.00
1
1
2
1
–18.62
1
–14.67
1
—
Operating Frequency φ (MHz)
4.9152
Error
3.6864
Error
4
5
Bit Rate
(bits/s)
Error
(%)
Error
(%)
n
2
1
1
0
0
0
0
0
0
—
0
N
(%)
n
2
1
1
0
0
0
0
0
0
0
0
N
n
2
1
1
0
0
0
0
0
0
0
0
N
(%)
n
2
2
1
1
0
0
0
0
0
0
0
N
110
64
0.70
70
0.03
86
0.31
88
64
–0.25
0.16
150
191 0.00
95 0.00
191 0.00
207 0.16
103 0.16
207 0.16
103 0.16
255 0.00
127 0.00
255 0.00
127 0.00
300
129 0.16
64 0.16
129 0.16
600
1200
2400
4800
9600
19200
31250
38400
[Legend]
95
47
23
11
5
0.00
0.00
0.00
0.00
0.00
—
51
25
12
6
0.16
0.16
0.16
–6.99
0.00
8.51
63
31
15
7
0.00
0.00
0.00
0.00
–1.70
0.00
64
32
15
7
0.16
–1.36
1.73
1.73
0.00
1.73
—
2
3
4
4
0.00
2
3
3
: A setting is available but error occurs
Rev. 3.00 Sep. 10, 2007 Page 297 of 528
REJ09B0216-0300