Section 16 Serial Communication Interface 3 (SCI3)
External
clock
Internal clock (φ/64, φ/16, φ/4, φ)
SCK3
Baud rate generator
BRC
BRR
Clock
SMR
SCR3
SSR
Transmit/receive
control circuit
TXD
RXD
TSR
RSR
TDR
RDR
Interrupt request
(TEI, TXI, RXI, ERI)
[Legend]
RSR:
Receive shift register
RDR:
TSR:
TDR:
Receive data register
Transmit shift register
Transmit data register
Serial mode register
SMR:
SCR3: Serial control register 3
SSR:
BRR:
BRC:
Serial status register
Bit rate register
Bit rate counter
Figure 16.1 Block Diagram of SCI3
Rev. 3.00 Sep. 10, 2007 Page 287 of 528
REJ09B0216-0300