Section 13 Timer Z
TCNT write cycle
T1
T2
φ
TCNT address
WTCNT
(internal write signal)
TCNT input clock
TCNT
N
M
TCNT write data
Figure 13.53 Contention between TCNT Write and Increment Operations
3. Contention between GR Write and Compare Match: If a compare match occurs in the T2 state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure
13.54 shows the timing in this case.
GR write cycle
T1
T2
φ
GR address
WGR
(internal write signal)
N
N
N+1
TCNT
GR
M
GR write data
Disabled
Compare match
signal
Figure 13.54 Contention between GR Write and Compare Match
Rev. 3.00 Sep. 10, 2007 Page 269 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
