Section 13 Timer Z
3. Output Inverse Timing by TFCR: The output level can be inverted by inverting the OLS1 and
OLS0 bits in TFCR in reset synchronous PWM mode or complementary PWM mode. Figure
13.46 shows the timing.
T1
T2
φ
Address bus
TOER address
TFCR
Timer Z
output pin
Inverted
Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR
4. Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD,
POLC, and POLB bits in POCR in PWM mode. Figure 13.47 shows the timing.
T1
T2
φ
Address bus
POCR address
TFCR
Timer Z
output pin
Inverted
Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR
Rev. 3.00 Sep. 10, 2007 Page 264 of 528
REJ09B0216-0300
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