Section 13 Timer Z
Table 13.3 Initial Output Level of FTIOB0 Pin
TOB0
POLB
Initial Output Level
0
0
1
1
0
1
0
1
1
0
0
1
PWM mode
Select counter clock
Select counter clearing source
Set PWM mode
[1] Select the counter clock with bits TPSC2
to TOSC0 in TCR. When an external
clock is selected, select the external
clock edge with bits CKEG1 and CKEG0
in TCR.
[2] Use bits CCLR1 and CCLR0 in TCR to
select the counter clearing source.
[3] Select the PWM mode with bits PWMB0
to PWMD0 and PWMB1 to PWMD1 in
TPMR.
[1]
[2]
[3]
[4] Set the initial output value with bits
TOB0 to TOD0 and TOB1 to TOD1 in
TOCR.
[5] Set the output level with bits POLB to
POLD in POCR.
[6] Set the cycle in GRA, and set the duty in
the other GR.
[7] Enable or disable the timer output by
TOER.
[4]
[5]
[6]
[7]
[8]
Set initial output level
Select output level
Set GR
[8] Set the STR bit in TSTR to 1 and start
the counter operation.
Enable waveform output
Start counter operation
<PWM mode>
Figure 13.21 Example of PWM Mode Setting Procedure
Rev. 3.00 Sep. 10, 2007 Page 235 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
