Section 13 Timer Z
Figure 13.20 shows an example of synchronous operation. In this example, synchronous operation
has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare
match has been set as the channel 0 counter clearing source, and synchronous clearing has been set
for the channel 1 counter clearing source. In addition, the same input clock has been set as the
counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from
pins FTIOB0 and FTIOB1. At this time, synchronous presetting and synchronous operation by
GRA_0 compare match are performed by TCNT counters.
For details on PWM mode, see section 13.4.5, PWM Mode.
TCNT values
Synchronous clearing by GRA_0 compare match
GRA_0
GRA_1
GRB_0
GRB_1
H'0000
Time
FTIOB0
FTIOB1
Figure 13.20 Example of Synchronous Operation
13.4.5
PWM Mode
In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins
with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level
of the corresponding pin depends on the setting values of TOCR and POCR. Table 13.3 shows an
example of the initial output level of the FTIOB0 pin.
The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB
is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A.
When POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by
compare match A. In PWM mode, maximum 6-phase PWM outputs are possible.
Figure 13.21 shows an example of the PWM mode setting procedure.
Rev. 3.00 Sep. 10, 2007 Page 234 of 528
REJ09B0216-0300
RENESAS [ RENESAS TECHNOLOGY CORP ]
