12.2
12.3
12.4
12.5
12.6
12.1.1
Features........................................................................................................... 237
12.1.2
Block Diagram................................................................................................ 238
12.1.3
Input Pins ........................................................................................................ 239
12.1.4
Register Configuration.................................................................................... 240
Register Descriptions...................................................................................................... 241
12.2.1
A/D Data Registers A to D (ADDRA to ADDRD)........................................ 241
12.2.2
A/D Control/Status Register (ADCSR) .......................................................... 242
12.2.3
A/D Control Register (ADCR) ....................................................................... 244
CPU Interface ................................................................................................................. 245
Operation ........................................................................................................................ 246
12.4.1
Single Mode (SCAN = 0) ............................................................................... 246
12.4.2
Scan Mode (SCAN = 1).................................................................................. 248
12.4.3
Input Sampling and A/D Conversion Time .................................................... 250
12.4.4
External Trigger Input Timing........................................................................ 251
Interrupts ........................................................................................................................ 251
Usage Notes .................................................................................................................... 252
Section 13
13.1
RAM
............................................................................................................. 253
13.2
Overview ........................................................................................................................ 253
13.1.1
Block Diagram................................................................................................ 253
13.1.2
RAM Enable Bit (RAME) in System Control Register (SYSCR) ................. 254
Operation ........................................................................................................................ 254
13.2.1
Expanded Modes (Modes 1 and 2) ................................................................. 254
13.2.2
Single-Chip Mode (Mode 3)........................................................................... 254
Section 14
14.1
14.2
ROM
.............................................................................................................. 255
14.3
14.4
Overview ........................................................................................................................ 255
14.1.1
Block Diagram................................................................................................ 256
PROM Mode................................................................................................................... 257
14.2.1
PROM Mode Setup......................................................................................... 257
14.2.2
Socket Adapter Pin Assignments and Memory Map...................................... 257
PROM Programming ...................................................................................................... 260
14.3.1
Programming and Verifying ........................................................................... 260
14.3.2
Notes on Programming ................................................................................... 264
14.3.3
Reliability of Programmed Data..................................................................... 264
14.3.4
Erasing of Data ............................................................................................... 265
Handling of Windowed Packages................................................................................... 266
Section 15
15.1
15.2
Power-Down State
.................................................................................... 267
Overview ........................................................................................................................ 267
15.1.1
System Control Register (SYSCR)................................................................. 268
Sleep Mode ..................................................................................................................... 269
15.2.1
Transition to Sleep Mode................................................................................ 269
RENESAS [ RENESAS TECHNOLOGY CORP ]
