8.3
8.4
8.5
8.6
8.7
8.2.4
Timer Interrupt Enable Register (TIER)......................................................... 131
8.2.5
Timer Control/Status Register (TCSR) .......................................................... 133
8.2.6
Timer Control Register (TCR)........................................................................ 135
8.2.7
Timer Output Compare Control Register (TOCR)......................................... 137
CPU Interface ................................................................................................................. 139
Operation ........................................................................................................................ 142
8.4.1
FRC Incrementation Timing........................................................................... 142
8.4.2
Output Compare Timing................................................................................. 144
8.4.3
FRC Clear Timing .......................................................................................... 145
8.4.4
Input Capture Timing ..................................................................................... 146
8.4.5
Timing of Input Capture Flag (ICF) Setting................................................... 149
8.4.6
Setting of Output Compare Flags A and B (OCFA and OCFB) .................... 150
8.4.7
Setting of FRC Overflow Flag (OVF) ............................................................ 151
Interrupts ........................................................................................................................ 151
Sample Application ........................................................................................................ 152
Usage Notes .................................................................................................................... 153
Section 9
9.1
8-Bit Timers
................................................................................................ 159
9.2
9.3
9.4
9.5
9.6
Overview ........................................................................................................................ 159
9.1.1
Features........................................................................................................... 159
9.1.2
Block Diagram................................................................................................ 160
9.1.3
Input and Output Pins ..................................................................................... 161
9.1.4
Register Configuration.................................................................................... 161
Register Descriptions...................................................................................................... 162
9.2.1
Timer Counter (TCNT)................................................................................... 162
9.2.2
Time Constant Registers A and B (TCORA and TCORB) ............................ 162
9.2.3
Timer Control Register (TCR)........................................................................ 163
9.2.4
Timer Control/Status Register (TCSR) .......................................................... 166
9.2.5
Serial/Timer Control Register (STCR)........................................................... 168
Operation ........................................................................................................................ 169
9.3.1
TCNT Incrementation Timing........................................................................ 169
9.3.2
Compare Match Timing.................................................................................. 171
9.3.3
External Reset of TCNT ................................................................................. 173
9.3.4
Setting of TCSR Overflow Flag (OVF).......................................................... 173
Interrupts ........................................................................................................................ 174
Sample Application ........................................................................................................ 174
Usage Notes .................................................................................................................... 175
9.6.1
Contention between TCNT Write and Clear ................................................. 175
9.6.2
Contention between TCNT Write and Increment .......................................... 176
9.6.3
Contention between TCOR Write and Compare-Match ............................... 177
9.6.4
Contention between Compare-Match A and Compare-Match B ................... 178
9.6.5
Incrementation Caused by Changing of Internal Clock Source ..................... 178
RENESAS [ RENESAS TECHNOLOGY CORP ]
