Table 1.1 SH7709S Features
Item
Features
CPU
•
•
•
•
Original Renesas Technology SuperH architecture
Object code level with SH-1, SH-2, and SH-3 Series
32-bit internal data bus
General-register files
Sixteen 32-bit general registers (eight 32-bit shadow registers)
Eight 32-bit control registers
Four 32-bit system registers
•
RISC-type instruction set
Instruction length: 16-bit fixed length for improved code efficiency
Load-store architecture
Delayed branch instructions
Instruction set based on C language
Instruction execution time: one instruction/cycle for basic instructions
Logical address space: 4 Gbytes
•
•
•
•
•
Space identifier ASID: 8 bits, 256 logical address space
Five-stage pipeline
Clock pulse
generator (CPG)
Clock mode: An input clock can be selected from the external input (EXTAL
or CKIO) or crystal oscillator.
•
Three types of clocks generated:
CPU clock: 1–24 times the input clock, maximum 200 MHz
Bus clock: 1–4 times the input clock, maximum 66.67 MHz
Peripheral clock: 1/4–4 times the input clock, maximum 33.34 MHz
Power-down modes:
•
Sleep mode
Standby mode
Module standby mode
•
•
•
•
•
•
One-channel watchdog timer
Memory
management
unit (MMU)
4 Gbytes of address space, 256 address spaces (ASID 8 bits)
Page unit sharing
Supports multiple page sizes: 1, 4 kbytes
128-entry, 4-way set associative TLB
Supports software selection of replacement method and random-replacement
algorithms
Rev. 5.00, 09/03, page 2 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
