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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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7.3.6  
PC Trace  
1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, repeat, and  
interrupt) is generated, the address from which the branch source address can be calculated and  
the branch destination address are stored in BRSR and BRDR, respectively. The branch  
address and the pointer, which corresponds to the branch, are included in BRSR.  
2. The branch address before branch occurs can be calculated from the address and the pointer  
stored in BRSR. The expression from BSA (the address in BRSR), PID (the pointer in BRSR),  
and IA (the instruction address before branch occurs) is as follows: IA = BSA – 2 * PID.  
Notes are needed when an interrupt (a branch) is issued before the branch destination  
instruction is executed. In case of the next figure, the instruction “Exec” executed immediately  
before branch is calculated by IA = BSA – 2 * PID. However, when branch “branch” has delay  
slot and the destination address is 4n + 2 address, the address “Dest” which is specified by  
branch instruction is stored in BRSR (Dest = BSA). Therefore, as IA = BSA – 2 * PID is not  
applied to this case, this PID is invalid. The case where BSA is 4n + 2 boundary is applied  
only to this case and then some cases are classified as follows:  
Exec:branch Dest  
Dest:instr  
(not executed)  
interrupt  
Int: interrupt routine  
If the PID value is odd, instruction buffer indicates PID+2 buffer. However, these expressions  
in this table are accounted for it. Therefore, the true branch source address is calculated with  
BSA and PID values stored in BRSR.  
3. The branch address before branch occurrence, IA, has different values due to some kinds of  
branch.  
a. Branch instruction  
The branch instruction address  
b. Interrupt  
The last instruction executed before interrupt  
The top address of interrupt routine is stored in BRDR.  
4. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the  
address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read  
BRSR and BRDR in order, the queue only shifts after BRDR is read. When reading BRDR,  
longword access should be used. Also, the PC trace has a trace pointer, which initially points  
to the bottom of the queues. The first pair of branch addresses will be stored at the bottom of  
the queues, then push up when next pairs come into the queues. The trace pointer will points to  
the next branch address to be executed, unless it got push out of the queues. When the branch  
address has been executed, the trace pointer will shift down to next pair of addresses, until it  
Rev. 5.00, 09/03, page 173 of 760  
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