6.3.6
Interrupt Request Register 0 (IRR0)
IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5
and PINT0 to PINT15. This register is initialized to H'00 by a power-on reset or manual reset, but
is not initialized in standby mode.
Bit:
7
6
5
4
3
2
1
0
PINT0R PINT1R IRQ5R IRQ4R IRQ3R IRQ2R IRQ1R IRQ0R
Initial value:
R/W:
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
When clearing an IRQ5R–IRQ0R bit to 0, read the bit while bit set to 1, and then write 0. In this
case, 0 should be written only to the bits to be cleared and 1 to the other bits. The contents of the
bits to which 1 is written do not change.
Bit 7—PINT0 to PINT7 Interrupt Request (PINT0R): Indicates whether there is interrupt
request input to pins PINT0 to PINT7.
Bit 7: PINT0R Description
0
1
No interrupt request to pins PINT0 to PINT7
Interrupt to pins PINT0 to PINT7
(Initial value)
Bit 6—PINT8 to PINT15 Interrupt Request (PINT1R): Indicates whether there is interrupt
request input to pins PINT8 to PINT15.
Bit 6: PINT1R Description
0
1
No interrupt request input to pins PINT8 to PINT15
Interrupt request input to pins PINT8 to PINT15
(Initial value)
Bit 5—IRQ5 Interrupt Request (IRQ5R): Indicates whether there is interrupt request input to
the IRQ5 pin. When edge detection mode is set for IRQ5, an interrupt request is cleared by
clearing the IRQ5R bit.
Bit 5: IRQ5R
Description
0
1
No interrupt request input to IRQ5 pin
Interrupt request input to IRQ5 pin
(Initial value)
Rev. 5.00, 09/03, page 138 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
