Td3
Td4
Tpr
Tpc
Tr
Trw
Tc1
Tc2
Tc3
Tc4/Td1
Td2
CKIO
tAD
tAD
tAD
BANK
Row
tAD
Precharge-sel
Address
Row
Row
H/L
c0
tCSD
tCSD
tRWD tRWD
RD/
tRASD tRASD tRASD
tRASD
tCASD2
tCASD2
tCASD2
tDQMD
tDQMD
DQMn
tRDS
tRDH
D63–D0
(read)
d0
d1
d2
d3
tWDD
tWDD
D63–D0
(write)
tBSD tBSD
tDACD
tDACD
tDACD
DACKn
(SA: IO ← memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.26 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001, CAS Latency = 3)
Rev. 6.0, 07/02, page 888 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
