T1
T2
CKIO
tAD
tAD
A25–A0
tCSD
tCSD
tRWD
tRWD
RD/
tRSD
tRSD
tRSD
tRDS
tRDH
D63–D0
(read)
tWED1
tWEDF
tWEDF
tWDD
tWDD
tWDD
D63–D0
(write)
tBSD
tBSD
tDACD
tDACD
tDACD
DACKn
(SA: IO ← memory)
tDACDF
tDACDF
DACKn
(SA: IO → memory)
tDACD
tDACD
DACKn
(DA)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.15 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
Rev. 6.0, 07/02, page 877 of 986