Table 22.35 Bus Timing (3)
HD6417750
F167
HD6417750
VF128
HD6417750
F167I
HD6417750
BP200M
1
2
3
*
*
*
Item
Symbol Min Max
Min Max
Min Max Unit Notes
Address delay time tAD
1.3
1.3
1.3
1.3
1.3
3.5
10
10
10
10
10
—
1.3
1.3
1.3
1.3
1.3
3.5
8
1.2
1.2
1.2
1.2
1.2
3
6
ns
ns
ns
ns
ns
ns
%6 delay time
&6 delay time
5: delay time
5' delay time
tBSD
8
6
tCSD
tRWD
tRSD
tRDS
8
6
8
6
8
6
Read data setup
time
—
—
Read data hold
time
tRDH
1.5
—
—
1.5
—
—
8
1.5
—
—
6
ns
ns
:( delay time
tWEDF
10
Relative to CKIO falling
edge
(falling edge)
:( delay time
tWED1
tWDD
1.3
1.3
10
10
1.3
1.3
8
8
1.2
1.2
6
6
ns
ns
Write data delay
time
5'< setup time
5'< hold time
tRDYS
tRDYH
tRASD
tCASD1
tCASD2
tCKED
tDQMD
3.5
1.5
1.3
1.3
1.3
0.5
1.3
1.3
3.5
1.5
1.3
—
—
10
10
10
10
10
10
—
—
10
3.5
1.5
1.3
1.3
1.3
0.5
1.3
1.3
3.5
1.5
1.3
—
—
8
3
—
—
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.5
1.2
1.2
1.2
0.5
1.2
1.2
3
5$6 delay time
&$6 delay time 1
&$6 delay time 2
CKE delay time
DQM delay time
8
6
DRAM
8
6
SDRAM
SDRAM
SDRAM
MPX
8
6
8
6
)5$0( delay time tFMD
8
6
,2,649 setup time
,2,649 hold time
tIO16S
—
—
8
—
—
6
PCMCIA
PCMCIA
PCMCIA
tIO16H
1.5
1.2
,&,2:5 delay time tICWSDF
(falling edge)
,&,25' delay time tICRSD
1.3
1.3
1.3
10
10
10
1.3
1.3
1.3
8
8
8
1.2
1.2
1.2
6
6
6
ns
ns
ns
PCMCIA
DACK delay time
tDACD
DACK delay time
(falling edge)
tDACDF
Relative to CKIO falling
edge
Rev. 6.0, 07/02, page 875 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
