Exception/interrupt
generation
Hardware operation
SPC ← PC
SSR ← SR
SR.BL ← B'1
SR.MD ← B'1
SR.RB ← B'1
Exception
Trap
Exception/
interrupt/trap?
Interrupt
EXPEVT ← H'160
TRA ← TRAPA (imm)
EXPEVT ← exception code
INTEVT ← interrupt code
SGR ← R15
No
Yes
Reset exception?
No
Yes
(BRCR.UBDE == 1) &&
(user break exception)?
PC ← DBR
PC ← VBR + vector offset
PC ← H'A0000000
Exception service routine
Debug program
R15 ← SGR
(STC instruction)
Execute RTE instruction
PC ← SPC
SR ← SSR
End of exception
operations
Figure 20.2 User Break Debug Support Function Flowchart
Rev. 6.0, 07/02, page 794 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
