Multi-
Multi-
Multi-
Start
bit
Data
proces- Stop
sor bit bit
Start
bit
Data
proces- Stop Start
Data
proces- Stop
sor bit bit
1
1
sor bit bit
bit
Serial
data
Idle state
(mark state)
0
D0 D1
D7
1
1
0
D0 D1
D7
0
1
0
D0 D1
D7
0
TDRE
TEND
Data written to SCTDR1
and TDRE flag cleared
to 0 by TXI interrupt
handler
TXI interrupt
request
One frame
TEI interrupt
request
MPBT bit cleared to 0, data
written to SCTDR1, and
TDRE flag cleared to 0 by
TEI interrupt handler
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception: Figure 15.15 shows a sample flowchart for
multiprocessor serial reception.
Use the following procedure for multiprocessor serial data reception after enabling the SCI for
reception.
Rev. 6.0, 07/02, page 638 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
