Tpr
Tpc
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Trw1
Trw1
Trw1
CKIO
Bank
Row
Precharge-sel
Address
Row
Row
H/L
c1
RD/
DQMn
D63–D0
(read)
c1
c2
c3
c4
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.37 Burst Write Timing (Different Row Addresses)
Pipelined Access: When the RASD bit is set to 1 in MCR, pipelined access is performed between
an access by the CPU and an access by the DMAC, or in the case of consecutive accesses by the
DMAC, to provide faster access to synchronous DRAM. As synchronous DRAM is internally
divided into two or four banks, after a READ or WRIT command is issued for one bank it is
possible to issue a PRE, ACTV, or other command during the CAS latency cycle or data latch
cycle, or during the data write cycle, and so shorten the access cycle.
When a read access is followed by another read access to the same row address, after a READ
command has been issued, another READ command is issued before the end of the data latch
cycle, so that there is read data on the data bus continuously. When an access is made to another
Rev. 6.0, 07/02, page 428 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
