Table 8.2 Parallel-Executability
2nd Instruction
MT
O
EX
O
X
BR
O
O
X
LS
O
O
O
X
FE
O
O
O
O
X
CO
X
1st
Instruction
MT
EX
BR
LS
O
X
O
O
O
O
X
X
O
O
O
X
X
FE
CO
O
O
X
X
X
X
X
O: Can be executed in parallel
X: Cannot be executed in parallel
8.3
Execution Cycles and Pipeline Stalling
There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware
unit operates on one of these clocks, as follows:
•
•
•
I-clock: CPU, FPU, MMU, caches
B-clock: External bus controller
P-clock: Peripheral units
The frequency ratios of the three clocks are determined with the frequency control register
(FRQCR). In this section, machine cycles are based on the I-clock unless otherwise specified. For
details of FRQCR, see section 10, Clock Oscillation Circuits.
Instruction execution cycles are summarized in table 8.3. Penalty cycles due to a pipeline stall or
freeze are not considered in this table.
•
•
Issue rate: Interval between the issue of an instruction and that of the next instruction
Latency: Interval between the issue of an instruction and the generation of its result
(completion)
•
•
•
•
Instruction execution pattern (see figure 8.2)
Locked pipeline stages (see table 8.3)
Interval between the issue of an instruction and the start of locking (see table 8.3)
Lock time: Period of locking in machine cycle units (see table 8.3)
Rev. 6.0, 07/02, page 204 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
