4.6.1
IC Address Array
The IC address array is allocated to addresses H'F000 0000 to H'F0FF FFFF in the P4 area. An
address array access requires a 32-bit address field specification (when reading or writing) and a
32-bit data field specification. The way and entry to be accessed is specified in the address field,
and the write tag and V bit are specified in the data field.
In the address field, bits [31:24] have the value H'F0 indicating the IC address array, the way is
specified by bit [13], and the entry by bits [12:5]. CCR.IIX has no effect on this entry
specification. The address array bit [3] association bit (A bit) specifies whether or not association
is performed when writing to the IC address array. As only longword access is used, 0 should be
specified for address field bits [1:0].
In the data field, the tag is indicated by bits [31:10], and the V bit by bit [0]. As the IC address
array tag is 19 bits in length, data field bits [31:29] are not used in the case of a write in which
association is not performed. Data field bits [31:29] are used for the virtual address specification
only in the case of a write in which association is performed.
The following three kinds of operation can be used on the IC address array:
1. IC address array read
The tag and V bit are read into the data field from the IC entry corresponding to the way and
the entry set in the address field. In a read, associative operation is not performed regardless of
whether the association bit specified in the address field is 1 or 0.
2. IC address array write (non-associative)
The tag and V bit specified in the data field are written to the IC entry corresponding to the
way and the entry set in the address field. The A bit in the address field should be cleared to 0.
3. IC address array write (associative)
When a write is performed with the A bit in the address field set to 1, the tag for each of the
ways stored in the entry specified in the address field is compared with the tag specified in the
data field. The way number set by bit [13] is not used. If the MMU is enabled at this time,
comparison is performed after the virtual address specified by data field bits [31:10] has been
translated to a physical address using the ITLB. If the addresses match and the V bit for that
way is 1, the V bit specified in the data field is written into the IC entry. In other cases, no
operation is performed. This operation is used to invalidate a specific IC entry. If an ITLB
miss occurs during address translation, or the comparison shows a mismatch, an interrupt is
not generated, no operation is performed, and the write is not executed. If an instruction TLB
multiple hit exception occurs during address translation, processing switches to the instruction
TLB multiple hit exception handling routine.
Rev. 6.0, 07/02, page 117 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
