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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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The following two kinds of operation can be used on the OC data array:  
1. OC data array read  
Longword data is read into the data field from the data specified by the longword specification  
bits in the address field in the OC entry corresponding to the entry set in the address field.  
2. OC data array write  
The longword data specified in the data field is written for the data specified by the longword  
specification bits in the address field in the OC entry corresponding the entry set in the address  
field. This write does not set the U bit to 1 on the address array side.  
31  
24 23  
14 13  
5 4  
2 1 0  
Address field  
Data field  
1 1 1 1 0 1 0 1  
Entry  
L
31  
0
Longword data  
L : Longword specification bits  
: Reserved bits (0 write value, undefined read value)  
Figure 4.11 Memory-Mapped OC Data Array  
4.6  
Memory-Mapped Cache Configuration (SH7750R)  
To enable the management of the IC and OC by software, a program running in the privileged  
mode is allowed to access their contents.  
The contents of IC can be read and written by using MOV instructions in a P2-area program  
running in the privileged mode. Operation is not guaranteed for access from a program in some  
other area. Any branching to other areas must take place at least 8 instructions after this MOV  
instruction.  
The contents of IC can be read and written by using MOV instructions in a P1- or P2-area  
program running in the privileged mode. Operation is not guaranteed if access is attempted from a  
program running in some other area. A branch to the P0, U0, or P3 area must be made at least 8  
instructions after this MOV instruction.  
The IC and OC are allocated to the P4 area of the physical memory space. The address and data  
arrays of both the IC and OC are only accessible by their data fields. Longword operations must  
be used. Instruction fetches from these areas are not possible. For reserved bits, a write value of 0  
should be specified; values read from such bits are undefined. Note that, in the SH7750/SH7750S-  
compatible mode, the configuration of the SH7750R’s memory-mapped cache is the same as that  
of the SH7750 or SH7750S.  
Rev. 6.0, 07/02, page 116 of 986  
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