APPENDIX
Appendix 1. Memory assigment in SFR area
Access characteristics
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
RW
RO
WO
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
State immediately after reset
: “0” immediately after reset.
: “1” immediately after reset.
: Undefined immediately after
reset.
0
1
?
: Always “0” at reading.
0
1
?
0
: Always “1” at reading.
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
Register name
Address
Access characteristics
State immediately after reset
b7
b0
b7
b0
RW
RW
WO
0016
Count start register 0
4016
4116
4216
4316
4416
0
0
0
0
0
0
?
0
0
0
0
0
0
0
0
Count start register 1
One-shot start register 0
One-shot start register 1
RW
RW
0
?
?
0
0
0
0
0
WO
RW
0
0
0
0
0
0
0
0
0
Up-down register 0
0
0
WO
0
0
RW
4516 Timer A clock division select register
RW
4616
(Note 5)
(Note 5)
?
?
?
?
?
Timer A0 register
4716
4816
(Note 5)
(Note 5)
(Note 5)
(Note 5)
RW
Timer A1 register
4916
4A16
Timer A2 register
4B16
?
?
?
?
?
?
?
?
?
?
4C16
Timer A3 register
4D16
RW
(Note 5)
(Note 5)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
(Note 6)
RW
4E16
Timer A4 register
4F16
5016
Timer B0 register
5116
5216
Timer B1 register
5316
5416
Timer B2 register
?
5516
Timer A0 mode register
5616
Timer A1 mode register
5716
Timer A2 mode register
5816
5916
5A16
5B16
5C16
5D16
5E16
5F16
0016
0016
0016
0016
RW
RW
RW
RW
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Processor mode register 0
Processor mode register 1
0016
(Note 7)
(Note 7)
(Note 7)
RW
RW
0
0
0
0
0
0
0
0
0
0
?
?
?
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
RW
RW
RW WO
RW
RW
RW
RW
0
Notes 5: The access characteristics at addresses 4616 to 4B16, 4E16, and 4F16 vary according to the timer A’s operating
mode. (Refer to “CHAPTER 7. TIMER A.”)
6: The access characteristics at addresses 5016 to 5516 vary according to the timer B’s operating mode. (Refer to
“CHAPTER 8. TIMER B.”)
7: The access characteristics for bit 5 at addresses 5B16 to 5D16 vary according to the timer B’s operating mode.
(Refer to “CHAPTER 8. TIMER B.”)
7906 Group User’s Manual Rev.2.0
20-4
RENESAS [ RENESAS TECHNOLOGY CORP ]
