SERIAL I/O
11.4 Clock asynchronous serial I/O (UART) mode
✕
Error-permitted range of transfer baud
During reception, the receive data input to the RxD pin is taken at the rising edge of the transfer
i
clock. (Refer to section “11.4.6 Receive operation.”) Accordingly, in order to receive data correctly,
the stop bit must be input when the transfer clock of one-set receive data rises last. Figure 11.4.1
shows the relationship between the transfer clock and receive data.
<1ST-8DATA-1SP>
When the transfer rate of
the receive data is faster
SP
ST
ST
D0
D7
than the rate of the transfer
clock on the receiver side
RxD
i
(Receive data)
When the transfer rate of
the receive data is slower
than the rate of the transfer
clock on the receiver side
D7
SP
D0
SP must be detected at
this last rising edge of
the transfer clock.
At the falling edge of ST, the transfer clock is
generated, and reception starts.
Transfer clock
(Receiver side)
1 clock
8 clocks
9.5 clocks
1 clock
✕
ST : Start bit
SP : Stop bit
✕ 1 period of BRGi’s count source (Maximum)
According to the condition of the input timing,
a maximum of this period (✕) can be omitted.
Fig. 11.4.1 Relationship between transfer clock and receive data
Accordingly, the transfer rate of the receiver and transmitter sides must satisfy the following formula
in order to receive data correctly.
1
Bt
1
F
1
Br
1
F
1
Bt
✕✕(b – 1) +
<
✕✕b
<
✕✕(b – 0.5) +
Br: Transfer rate on receiver side (bps)
Bt: Transfer rate on transmitter side (bps)
F : BRGi’s count source frequency on receiver side (Hz)
b : Entire bit number of one-set data
(ex: 12 bits in the case of 1ST-8DATA-1PAR-2SP; See Figure 11.4.2.)
Be sure to satisfy the above formula, and set the timing with enough margin. Also, the user shall
make sufficient evaluation before actually using it.
7906 Group User’s Manual Rev.2.0
11-38
RENESAS [ RENESAS TECHNOLOGY CORP ]
