THREE-PHASE WAVEFORM MODE
10.4 Three-phase mode 1
Timers A0 through A3 are inactive.
Setting of timers A0 through A2 to one-shot pulse mode
b7
b0
b7
b0
Count start register 0
Timer A0/A1/A2 mode register
0
0
0
0
(address 4016
)
0
1
1
0
1
0
(addresses 5616 to 5816
)
Stops counting in timer A0.
Stops counting in timer A1.
Stops counting in timer A2.
Stops counting in timer A3.
Count source select bits
(See Table 7.2.3.)
Setting of timer A3 to timer mode
b7
b0
Timer A3 mode register
0
0
0
0
0
0
(address 5916
)
Setting of waveform output mode register
b7
b0
Waveform output mode register
Count source select bits
(See Table 7.2.3.)
0
1
❈
1
1
0
0
(address A616
)
Three-phase mode 1
Three-phase output polarity
set buffer (Note)
0 : “H” output
1 : “L” output
Setting of timer A0/A1/A2/A3 interrupt request to “disabled”
Dead-time timer trigger
select bit
Falling edge of one-shot
pulse
b7
b0
Timer A0/A1/A2/A3 interrupt
control register
0
0
0
0
(addresses 7516 to 7816
)
Waveform output is disabled.
Interrupt disabled
❈ : It may be either “0” or “1.”
No Interrupt request
Setting of dead-time timer
b7
b0
Dead-time timer
(address A716
)
Setting of timer A3 carrier wave’s period
A value in the range from “0016” to “FF16
is set.
”
(b15)
b7
(b8)
b0 b7
b0
Timer A3 register
(addresses 4D16, 4C16
)
A value in the range from “000016” to
“FFFF16” is set.
Setting of three-phase output data register 0, 1
b7
b0
Three-phase output data register 0
❈ ❈ ❈
0
0
0
Setting of output width of each phase of timers A0
through A2
(address A816
)
Released from W-phase output
fixation.
Released from V-phase output
fixation.
(b15)
b7
(b8)
b0 b7
Timer A0 register
(addresses 4716, 4616
Timer A1 register
b0
)
)
(addresses 4916, 4816
Timer A2 register
Released from U-phase output
fixation.
(addresses 4B16, 4A16
Timer A0 register
(addresses D116, D016
Timer A1 register
(addresses D316, D216
Timer A2 register
(addresses D516, D416
)
1
Clock-source-of-dead-time-timer
select bits
b7 b6
)
)
)
1
0 0 : f
0 1 : f
1 0 : f
2
2
2
/2
/4
1
A value in the range from “000016” to
“FFFF16” is set.
b7
b0
Three-phase output data register 1
❈ ❈
❈ ❈ ❈ ❈
(address A916
)
Interrupt request interval set bit
0 : Every second time
1 : Every forth time
Internal output for stabilization of output level
b7
b0
Count start register 0
(address 4016
Interrupt validity output select bit
0 : At each even-numbered
underflow of timer A3
1 : At each odd-numbered
underflow of timer A3
1
1
1
1
)
Starts counting in timer A0.
Starts counting in timer A1.
Starts counting in timer A2.
Starts counting in timer A3.
❈ : It may be either “0” or “1.”
Continues to the next page.
Note: The contents of the three-phase output polarity set buffer
are reversed once before the output level is stabilized.
Therefore, at this time, be sure to set the reversed level of
the level which the user desires to output.
Fig. 10.4.1 Initial setting example for registers relevant to three-phase mode 1 (1)
7906 Group User’s Manual Rev.2.0
10-27
RENESAS [ RENESAS TECHNOLOGY CORP ]
