THREE-PHASE WAVEFORM MODE
10.2 Block description
10.2.1 Waveform output mode register
Figure 10.2.2 shows the structure of the waveform output mode register (the three-phase waveform mode).
Note that writing to bits 0 through 6 of this register must be performed when the counting in timers A0
through A3 is halts.
b7 b6 b5 b4 b3 b2 b1 b0
Waveform output mode register (Address A616
)
X
1 0 0
Bit
0
Bit name
Function
At reset R/W
b2 b1 b0
0
0
0
0
RW
RW
RW
RW
Waveform output select bits
1 0 0 : Three-phase waveform mode
(Note 1)
1
2
3
0 : “H” output
1 : “L” output
Three-phase output polarity set buffer
(Valid in three-phase mode 1) (Note 2)
0
RW
0 : Three-phase mode 0
1 : Three-phase mode 1
4
Three-phase mode select bit
0
0
RW
RW
5
6
Invalid in the three-phase waveform mode.
0: Both falling and rising edges of one-shot
Dead-time timer trigger select bit
(Note 3)
pulse for timers A0 to A2
1: Only the falling edge of one-shot pulse for
timers A0 to A2
0 : Waveform output disabled
1 : Waveform output enabled
0
RW
7
Waveform output control bit
X: It may be either “0” or “1.”
Notes 1: When not using the pulse output mode and three-phase waveform mode, be sure to fix these bits to “000
2
.”
2: This bit is invalid in three-phase mode 0.
3: When the saw-tooth-wave modulation output is performed, be sure to fix this bit to “0.”
4: Writing to any of bits 0 to 6 must be performed while counting for timers A0 to A3 halts.
Fig. 10.2.2 Structure of waveform output mode register (three-phase waveform mode)
7906 Group User’s Manual Rev.2.0
10-5
RENESAS [ RENESAS TECHNOLOGY CORP ]
